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954 bytes added, 20:26, 12 August 2018
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XSAVE stands for similar x86 instruction [ <code>xsave</code>] which places extended processor state into a memory area. The saving can be initiated by any userspace application at any moment and size of the memory frame depends on processor features and may vary between different models. Thus if checkpoint and restore are done on different processors the next call to <code>xsave</code> may corrupt memory if sizes mismatch.
=== XSAVE frame size Helpers ===
Before fetching frame sizes one need to figure out if <code>xsave</code> is supported at all. There are several helpers we will refer onin this page
static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
native_cpuid(eax, ebx, ecx, edx);
=== Frame size ===
Run <code> cpuid(0x1, &eax, &ebx, &ecx, &edx)</code> and bits 26 and 27 are both set in <code>ecx</code> if <code>xsave</code> is supported (strictly speaking bit 27 is reserved for operating system which can clear it to indicate that instruction is disabled).
After that we can fetch maximal frame size which applications may use via <code>cpuid_count(0xd, 0, &eax, &ebx, &ecx, &edx)</code>, in result <code>ebx</code> will contain the size to keep currently enabled components of the frame and <code>ecx</code> will keep the value of maximal frame size. The maximal here means the size needed when all components are enabled (OS may disable some of components). === Enumerating frame components === To enumerate which components of the frame are enabled execute <code>cpuid_count(0xd, 0, &eax, &ebx, &ecx, &edx)</code>. Each component will have bit set to 1 in 64 bit mask <code>eax + ((uint64_t)edx << 32)</code> if enabled. Current list of known components are the following (numbers are the bit position): * <code>0</code>: x87 floating point registers* <code>1</code>: SSE registers* <code>2</code>: AVX registers* <code>3</code>: MPX bounds registers* <code>4</code>: MPX CSR* <code>5</code>: AVX-512 opmask* <code>6</code>: AVX-512 Hi256* <code>7</code>: AVX-512 ZMM_Hi256* <code>8</code>: Processor Trace* <code>9</code>: Protection Keys User registers* <code>10</code>: Hardware Duty Cycling

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