433
edits
Changes
no edit summary
* <code>10</code>: Hardware Duty Cycling
* <code>10</code>: Hardware Duty Cycling
Once the bit mask is obtained we have to walk over each bit set and call <code>cpuid_count(0xd, component, &eax, &ebx, &ecx, &edx)</code>, where <code>component</code> is the bit position we are interested in. In other words it should be from 0 to 10. The result of this call is sitting in <code>ebx</code> which represent offset of the component from the frame base address and <code>eax</code> which shows component size. Note that some of components are supervisor components and if <code>(ecx & 1) == 0</code> from the <code>cpuid_count</code> call above then its offset is undefined.
Once the bit mask is obtained we have to walk over each bit set and call <code>cpuid_count(0xd, component, &eax, &ebx, &ecx, &edx)</code>, where <code>component</code> is the bit position we are interested in. In other words it should be from 0 to 10. The result of this call is sitting in <code>ebx</code> which represent offset of the component from the frame base address and <code>eax</code> which shows component size. Note that some of components are supervisor components and if <code>(ecx & 1) == 0</code> from the <code>cpuid_count</code> call above then its offset should not be considered while size is still valid.
=== Potential memory corruption ===
When processes are dumped and restored on different cpu, the application may have remembered frame size on its own somewhere inside own code and in worst scenario it may allocate memory with size less than needed on different cpu, so the next call to <code>xsave</code> silently overwrite memory leading to sigsegv in best case.
Current criu implementation check for <code>cpuinfo</code> images to be compatible and size and features required to match. In turn some OS may mask some of the features with cpuid faulting engine but still all cpus in the pool should report same maximal size of the frame.